1. Field of the Invention
The present invention relates to an image processing system. More particularly, it relates to a first group of embodiments such as an outline correction circuit for correcting an outline of image information; a second group of embodiments such as a signal processing of video or image related devices, particularly, a pixel interpolation circuit and its applied devices for interpolating missed or omitted pixels; third and fourth groups of embodiments such as an interpolation devices for forming or producing missed or omitted data in a processing system of digital image signals or a transmission line, particularly, a pixel interpolation device relating to an image signal processing device such as a video printer or the like; and a fifth group of embodiments such as a multipicture formation device for forming one image from a plurality of reduced images to be used in a video printer, particularly, a multipicture formation device for improving an image quality by rising a thinning filter when an image is reduced, in an image processing system.
2. Description of the Related Arts
FIG. 65 illustrates a conventional outline correction circuit, for example, as disclosed in Japanese Patent Laid-Open No. Sho 61-71773. In FIG. 65, the outline correction circuit includes two registers 100 and 101, four multipliers 102, 103, 104 and 107, two adders 105 and 108 and a factor setting device 106. Input image data Pi are input to the outline correction circuit and output image data Po are output therefrom. In this case, Pi+1 and Pi+2 denote data delayed by one unit time and two unit times, respectively.
FIG. 66 shows a relationship between an input level and an output level of the multiplier 107 shown in FIG. 65.
Next, the operation of the outline correction circuit described above will now be described. The input image data Pi are input to the register 100 and the multiplier 102 and are delayed one unit time in the register 100, and the register 100 outputs one unit time delayed image data Pi+1 to the register 101, the multiplier 103 and the adder 108. The register 101 further delays the one unit time delayed image data Pi+1 to output two unit times delayed image data Pi+2 to the multiplier 104. The multiplier 102 multiplies a factor -1 to the image data Pi to output -Pi to the adder 105, and the multiplier 103 multiplies a factor 2 to the image data Pi+1 to output 2(Pi+1) to the adder 105. The multiplier 104 multiplies a factor -1 to the image data Pi+2 to output -(Pi+2) to the adder 105. The adder 105 adds the input data to output an addition result to the multiplier 107 and the factor setting device 106. The multiplier 107 multiplies a multiplication factor sent from the factor setting device 106 to the addition result sent from the adder 105 to output a multiplication result to the adder 108. In this case, the factor setting device 106 outputs the multiplication factor so that the multiplier 107 may keep the relationship between the input and output levels shown in FIG. 66. That is, when the output of the adder 105 is smaller than a predetermined value, the factor setting device 106 considers the input signal to be a noise and outputs a small multiplication factor so as to reduce the output. The adder 108 adds the output of the multiplier 107 to the output of the register 100 to output the outline emphasized image data Po.
In the conventional outline correction circuit, as described above, an outline emphasis to reduce a noise emphasis can be performed. However, a noise removal and a discrimination threshold value adjustment can not be carried out simultaneously, and thus a preferable image for a user can not be necessarily obtained.
FIG. 67 shows a conventional pixel interpolation circuit, for example, as disclosed in Japanese Patent Laid-Open No. Hei 2-131689. In FIG. 67, the pixel interpolation circuit is comprised of an interpolation data formation circuit 200, a pair of low pass filters (hereinafter referred to as "LPFs") 201a and 201b, a selector circuit 228, a correlative discrimination circuit 229 and a one line delay circuit 230 for delaying the input image data. The interpolation data formation circuit 200 includes registers 207, 208, 209 and 210, adders 211, 212 and 213 and 1/2 (half) multipliers 214, 215 and 216. The LPF 201a includes registers 202a, 203a and 205a and adders 204a and 206a, and the LPF 201b includes registers 202b, 203b and 205b and adders 204b and 206b. The correlative discrimination circuit 229 includes registers 217, 218, 219 and 220, subtracters 221, 222 and 223, absolute value circuits 224, 225 and 226, and a minimum value discrimination circuit 227.
Next, the operation of the above-described pixel interpolation circuit will now be described. The input image data Pi are input to the one line delay circuit 230 and are delayed one line therein. The input image data Pi are also input to the interpolation data formation circuit 200 and the LPF 201a, and the one one delayed image data output from the one line delay circuit 230 are input to the interpolation data formation circuit 200 and the LPF 201b. In the interpolation data formation circuit 200, by using the registers 207, 208, 209 and 210, the adders 211, 212 and 213 and the half multipliers 214, 215 and 216, for the interpolation pixel, addition averaging values in the upward, downward and inclined directions are calculated as interpolation data.
On the other hand, in the LPF 201a and the LPF 201b, by using the registers 202a, 203a, 205a, 202b, 203b and 205b and the adders 204a, 206a, 204b and 206b, horizontal low frequency components (hereinafter referred to as "horizontal low components") of the respective input image data are picked up and output to the correlative discrimination circuit 229. In the correlative discrimination circuit 229, by using the registers 217, 218, 219 and 220, the subtracters 221, 222 and 223, and the absolute value circuits 224, 225 and 226, differential absolute values in the upward, downward and inclined directions centering around the interpolation pixel are calculated. The calculated differential absolute values are input to the minimum value discrimination circuit 227, and the minimum value discrimination is performed therein. At this time, the direction of the minimum value is the most correlated direction, and thus the selector circuit 228 selects the interpolation data of the most correlated direction from the three outputs of the multipliers 214, 215 and 216 of the interpolation data formation circuit 200 and outputs the selected interpolation data as the output image data Po.
In the conventional pixel interpolation circuit, as described above, relating to an image whose signal frequency band is offset to the low side (hereinafter referred to as "low band image"), a correlative difference among the upward, downward and inclined directions is small, and hence an interpolation result with sufficient effects can not be obtained.
FIG. 68 shows a pixel interpolation device of color signals for use in a conventional video printer. In FIG. 68, the pixel interpolation device comprises a Y/C separation circuit 482 for separating a video signal input from an input terminal 481 into a luminance signal Y and a color signals C, an A/D (analog-digital) converter 483 for converting the separated analog color signal C into digital image data, a thinning switch 484 for thinning the conversion data every pixel, and an image memory 433 for storing the thinned conversion data to be output from an output terminal 485.
Next, the operation of the above-described pixel interpolation device will now be described. In FIG. 68, the analog color signals C separated in the Y/C separation circuit 482 are sampled by a sampling frequency 2 f sc (subcarrier frequency) in the A/D converter 483 to obtain sampled digital signals 512a. FIG. 69 shows a pixel arrangement of the signals 512a, wherein H represents a one pixel interval and V represents one line interval. Then, the signals 512a are thinned every pixel in the thinning switch 484 to obtain signals 512b. Since the thinned signals 512b are resampled signals every sampling clock f sc, the image information is reduced by half, and thus the capacity of the image memory 433 for storing the signals 512b can be reduced by half compared with a case for storing the signals 512a. FIG. 70 shows a pixel arrangement of the signals 512b, wherein X indicates an omitted or missed pixel by the sampling. The image memory 433 stores one frame of the signals 512b at a predetermined timing and outputs from the first line at a predetermined timing. At this time, no particular interpolation calculation for the omitted pixels is not carried out, and the just preceding data as the omitted pixel data can be simply used as it is.
In the conventional pixel interpolation device, as described above, no particular interpolation processing for the omitted pixels is performed and thus the image quality is largely deteriorated. Further, the border lines or outlines of the edges in the inclined direction are jagged.
FIG. 71 shows a conventional multipicture formation device for a vide printer. In FIG. 71, the multipicture formation device is comprised of an image memory 602 for storing one field of video signals input from an input terminal 601 (the video signals constituting one field by 1/60 sec and two fields by 1/30 sec and two fields constituting one frame or one picture), a thinning switch 608 for thinning the data read out of the image memory 602, a register 606 for storing one line of data of a multipicture, and a printer 607 for printing the image data.
Next, the operation of the multiimage frame formation device described above will now be described. The video signals input from the input terminal 601 are stored for one field in the image memory 602 at any timing, and in response to a request signal REQ output by the printer 607, the data are read line by line out of the image memory 602 in an interlaced manner. The readout data are thinned to 1/4 pixels by the thinning switch 608. As a result, by the above-described operation, as shown in FIG. 72, the data stored in the image memory 602 are thinned to 1/4 pixels and 1/2 line in the horizontal and vertical directions, respectively, to be compressed to 1/16 picture of data (one field of data are the half of the line numbers of one picture, as described above).
FIG. 73(a) shows a process for forming a multipicture by the compressed data. As shown in FIG. 73(a), one line of data are thinned to 1/4 pixels by the thinning switch 608, and the one line of thinned data are then stored into four core areas of the four-divided register 606. The printer 607 successively prints out the data stored in the register 606 as the one line of data and outputs the request signal REQ to the image memory 602 at the same time. The above-described operation is repeated until the one field of data stored in the image memory 602 are output four times to print out the same 16 multipicture, as shown in FIG. 73(b).
In the multipicture formation device, as described above, considerable aliasing noises occur in the thinned image data.